This invention relates to an information processing system including plural arithmetic units for implementing a high speed processing of instructions.
The implementation of high speed processing in recent years has brought about a system having an arithmetic section divided into a plurality of dedicated arithmetic units in many information processors. For example, there has been proposed a system having an arithmetic section divided into two units, i.e., a general instruction arithmetic unit (GU) for executing a fixed-point instruction, a decimal instruction etc. and a floating-point instruction arithmetic unit (FU) for executing a floating-point instruction at a high speed. A certain system may have an arithmetic unit divided into more sub-arithmetic units. In such an information processing system, if a conditional branch instruction is provided for which a judgement about the success or failure of a branch is determined by a condition code (CC) of a Program Status Word (PSW), and this CC is determined by an operation result, it is required that the CC be created by the corresponding arithmetic unit and be finally transferred to a CC part of a PSW. The transfer time of the CC from each arithmetic unit to branch judgement means influences the performance of the conditional branch instruction.
FIG. 1 shows a block diagram of an information processing system having two arithmetic units. In the figure, a main storage unit (MS) 1, a storage control unit (SCU) 2, and an instruction control unit (IU) 3 are usual ones, but an arithmetic unit 4 is characterized by having an general instruction arithmetic unit (GU) 5 and a floating-point instruction arithmetic unit (FU) 6.
FIG. 2 shows an example of the conventional construction of GU 5 and FU 6. In the figure, it is assumed that a general instruction arithmetic device 201 in GU 5 performs a fixed-point operation and a decimal operation while a floating-point instruction arithmetic device 210 in FU 6 performs a floating-point operation. CC creation circuits 202 and 211 respectively in GU 5 and FU 6 create CC's in accordance with the respective forms of instruction by using the results of the above operations. The CC's thus created are transferred via signal lines 203, 212 and loaded in a CC portion 205 of a PSW through a selector 204. In this example, the CC portion 205 of the PSW is placed in the GU 5, and the CC portion 205 in FU 6 is transferred to GU 5, but the CC portion 205 of the PWS may be placed in either unit. In either case, the CC's created in a plurality of units must be concentrated where a branch judging circuit 207 is present. The selector 204 acts as a circuit for selecting the CC of GU 5 (GU CC) in response to a fixed point/decimal instruction and for selecting the CC of FU 6 (FU CC) in response to a floating point instruction.
Concurrently with the storing of the CC of GU 5 or FU 6 into the CC portion 205 of the PSW, the CC of GU 5 or FU 6 is inputted to a branch judging circuit 207 through a selector 206. The selector 206 serves to select GU CC on signal line 203 when a GU CC change instruction which is executed in the GU 5 to change the previous CC (such as a fixed point addition instruction) exists immediately before a conditional branch instruction (BC instruction: Branch on Condition instruction), to select an FU CC on signal line 212 when an FU CC change instruction which is executed in the FU 6 to change the previous CC, (such as floating point addition instruction) exists and to select a CC of the PSW when another instruction exists. The CC on the signal line 212 or 203 is selected to speed up the branch judgement. The judgement result by a branch judgement circuit 207 is sent out to IU 3 through a branch judgement signal line 208. The IU 3 serves to allocate one instruction buffer (now shown) for each of a main instruction stream and a target instruction stream to speed up the processings upon the generation of a branch instruction. Such control method is known from U.S. Pat. No. 3,614,747. In the case of success of the branch, instruction fetching and instruction decoding in a main stream of the instruction (a stream including the BC instruction) are stopped, the instructions contained in the instruction buffer for the main stream are cancelled, and instruction decoding of the target stream is also started. Incidentally, it is assumed that instruction fetching from the target instruction has been started at the time of decoding of the BC instruction. On the other hand, in the case of failure of the branch, the instruction fetching from the target stream is stopped and the main stream of instructions is continued. These processings are controlled by a branch control circuit 209.
Meanwhile, a problem of the prior art is that since a branch judgement circuit is placed in the GU, a branch judgement is delayed by the time of transferring the CC from FU to GU when an FU CC change instruction exists immediately before a BC instruction, thereby reducing the performance of a BC instruction. This problem also applies in the case where the branch judgement circuit is provided in the FU.